With the continued flash memory scaling, particularly, NAND flash technology scaling, the conventional use of a fixed starting program voltage (Vstart) throughout the life cycle of a NAND flash memory device results in inefficient programming. Incremental Step Pulse Programming (ISPP) is a commonly used NAND program method to achieve balance between Vth distribution and program time (tPROG). FIG. 1 illustrates the ISPP scheme, and FIG. 2 shows the four threshold voltage distributions for a 2-bit per cell flash memory where L0 represents the erased state and L1, L2 and L3 represent 3 program states. The ISPP starts by applying a relatively low starting program voltage Vstart followed by a program verify PV operation. After that, the program voltage is increased by Vstep and another programing/verifying operation is carried out. This process is repeated until the target threshold voltage (L1, L2 or L3 in FIG. 2) is reached.
As FIG. 1 suggests, the number of program pulses can be calculated as follows:
      Number    ⁢                  ⁢    of    ⁢                  ⁢    Program    ⁢                  ⁢    Pluses    =                    V        final            -              V        start                    V      step      
As the above relationship indicates, the program time is fixed regardless of the lifecycle of the NAND flash memory. However, in general, the NAND program time is reduced as the number of program-erase (PE) cycles increases. Because of this phenomenon, a cycling guard band (program speed difference between the beginning of life (BOL) condition and the end of life (EOL) condition) needs to be accounted for in selecting an appropriate Vstart value. As is more clearly described with reference to FIG. 3 further below, the cycling guard band results in selection of a low (conservative) Vstart in order to avoid over-program (program overshoot) in the EOL scenario. Accordingly, the cycling guard band leads to BOL program time (tPROG) that is longer than necessary. This programming inefficiency is even more pronounced in flash technologies with greater than four levels, such as TLC with 8 states and QLC with 16 states.
The impact of the guard band on the selection of Vstart can be more clearly seen in FIG. 3. In FIG. 3, the three voltage distribution lines shown by dashed lines represent there different Vstart distributions corresponding to different stages in the program/erase (PE) life cycle of the flash memory. The first dashed line distribution next to L0 represents the start of life (SOL) distribution. The next one represents the middle of life (MOL) distribution and the far right dashed line represents the end of life (EOL) distribution of Vstart. These three distribution dashed lines are marked in FIG. 3 as SOL, MOL and EOL. As can be seen, with increasing PE cycles, the distribution of Vstart shifts higher. In other words, the programming of the NAND cell becomes easier and easier as the number of PE cycles increases. However, after the initial Vstart programing, the Vstart distribution should never extend beyond the distribution of the L1 state. This is illustrated by the dashed line distribution for Vstart marked in FIG. 3 as EOL. If the distribution of Vstart goes beyond the L1 state, an over-shot condition occurs and programming fails. Because of this, Vstart is set to a lower value to avoid the over-shot programming in the EOL condition. However, the lower Vstart value leads to slower than necessary programming during BOL to MOL cycles, thus resulting in excessively long overall programming performance. This programming inefficiency is even more pronounced in flash technologies with greater than four levels, such as TLC (8 levels) and QLC (16 levels). Thus, there is a need for more efficient programming techniques.